1. Field of the Invention
This invention relates generally to successive-approximation analog-to-digital (A/D) converters and, more particularly, to a metal-oxide-semiconductor (MOS) charge redistribution, successive-approximation A/D converter utilizing a half least significant bit shift.
2. Description of the Prior Art
Successive approximation analog-to-digital conversion is well known. For example, see U.S. Pat. Nos. 3,964,061; 3,949,395; 3,603,970; and 3,581,304. It involves the repeated division of the voltage range in half. In a three-bit system, for example, the system will first try 100 (half scale). Next, the system will try 010 (quarter scale) or 110 (three-quarter scale) depending on whether the first approximation was too large or too small. After three approximations, a three-bit representation of the unknown analog voltage is resolved. A more detailed discussion of successive approximation A/D converters may be found in Integrated Electronics: Analog and Digital Circuits and Systems, McGraw-Hill, Inc., 1972, page 667.
It is also known to use a sample-and-hold circuit in conjunction with an A/D converter. A capacitor (or capacitors) is charged with the unknown analog input voltage during a sample phase and retains the value during the conversion phase. The holding time is the length of time the circuit can hold a charge without dropping more than a specified percentage of its initial value. For an additional discussion of such circuits, see The Logic Handbook, Digital Equipment Corp., 1967 Edition, page 281.
Charge redistribution approaches to A/D conversion are known; e.g. U.S. Pat. No. 4,065,766. Further, the use of binary weighted capacitors is known; e.g. U.S. Pat. No. 3,836,906. In one known A/D conversion arrangement, a plurality of binary weighted capacitors are each charged by an unknown analog input signal. The common output of each of the capacitors is coupled to the input of a chopper stabilized comparator (a plurality of inverters each separated by capacitor) which, during the sample phase, is caused to assume an input voltage which is equal to its threshold voltage; i.e. a small variation at its input will cause the comparator output to switch. After the sample phase, the input to the comparator is left floating, i.e., no DC paths. Thereafter, signals from a successive approximation register are used to control a plurality of field-effect-transistor (FET) couplers to couple each of the binary weighted capacitors to either the high reference voltage (VRH, typically five volts in an NMOS system) or to a low reference voltage (VRL, typically ground). The analog input voltage, which may be as high as VRH, requires field-effect-transistor couplings to each of the capacitors.
It should be appreciated, that to pass either the analog input voltage or the high reference voltage to the various coupling field-effect-transistor coupling switches, it is necessary that the enabling voltage placed on the gate electrodes of the couplers be higher than the sum of the voltages being passed plus the FET threshold voltage. In a system in which the analog input voltage may be as high as the circuit supply voltage, a voltage boost circuit would be required in each case to achieve the required gate electrode voltages.
A second problem associated with the known circuit resides in the fact that a field-effect-transistor coupler has its current conducting path connected across the input and output of the comparator. When the high reference voltage is five volts and the low reference voltage is zero volts, and assuming an unknown analog input signal of five volts, the balanced comparator input node voltage (the comparator threshhold voltage) is typically two volts or less. Sampling is done on all binary weighted capacitors, and the first approximation connects the largest capacitor to VRH and all others to VRL. That is, the first approximation is 2.5 volts. Assuming neglible attenuation through the capacitors, the resulting redistribution of charge causes the comparator input voltage to drop by 2.5 volts (the analog input voltage minus the first approximation voltage), resulting in a voltage at the input of the comparator of minus 0.5 volts. This, however, tends to turn on the field-effect-transistor coupler across the first stage of the comparator causing leakage to occur at the comparator input node. Since the charge stored on this node is in essence the stored sample, accuracy is lost.
One analog-to-digital converter of the successive approximation type which solves the above described problems is described in U.S. patent application Ser. No. 148,097 filed May 9, 1980 and entitled "Analog-to-Digital Converter." In this system, an unknown analog input voltage is sampled only on the largest capacitor of a binary weighted capacitive ladder network. The conversion phase proceeds utilizing all the capacitance and only one half the reference voltage. The circuit requires only a single voltage boost circuit of the type described in U.S. Pat. No. 4,346,310 entitled "Voltage Booster Circuit." This A/D converter, however, suffers from the following disadvantage. As the unknown input voltage varies linearly, the digital output from the A/D converter is a step function. There are very few points on the step function which are coincident with the unknown input voltage, as indicated in FIG. 1A. In actuality, the digital output voltage contains an average error equivalent to one-half bit and a maximum error equivalent to one bit. This error is referred to as quantization error.
A successive-approximation analog-to-digital converter technique utilizing a hybrid resistor string and capacitor array is described in the International Solid State Circuits Conference Digest, 1979, pages 186-187. The resistive ladder is used to subdivide the voltage range from a high reference voltage (VRH) to a low reference (VRL). The most significant bits of the converted output are obtained using the resistors in a manner similar to the standard resistive string A/D method; i.e. determining the voltage subdivision which brackets the unknown voltage. The low order bits are then determined by a charge redistribution method using binary weighted capacitors. However, rather than using VRH and VRL in the low order phase, the voltages references used are the two voltages from the resistor string determined in the previous phase to bracket the unknown voltage. This circuit also suffers from the disadvantage of having a relatively high quantization error in the digital output representation of the unknown analog input voltage.